PackagePFC ControlStartup CurrentOperating CurrentTypeTSSOPLVTTLGTLP 50
GTLP8T306 |
RFQ for GTLP8T306 |
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| Technical/Catalog Information | GTLP8T306MTC |
| Vendor | Fairchild Semiconductor |
| Category | Integrated Circuits (ICs) |
| Logic Type | Transceiver, Non-Inverting |
| Package / Case | 24-TSSOP |
| Packaging | Tube |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 - Single |
| Operating Temperature | -40°C ~ 85°C |
| Voltage - Supply | 3.15 V ~ 3.45 V |
| Current - Output High, Low | 24mA, 24mA |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | GTLP8T306MTC GTLP8T306MTC |
| Product | Manufacturers | Pack | D/C | |||||
| GTLP8T306 | - | SSOP | - |
The GTLP8T306 is an 8-bit bus transceiver that providesLVTTL to GTLP signal level translation. The device pro-vides a high speed interface between cards operating atLVTTL logic levels and a backplane operating at GTLPlogic levels. High speed backplane operation is a directresult of GTLP's reduced output swing (<1V), reduced inputthreshold levels and output edge rate control. The edgerate control minimizes bus settling time. GTLP is a FairchildSemiconductor derivative of the Gunning Transceiver logic(GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal output edge-rate control andis process, voltage, and temperature (PVT) compensated.Its function is similar to BTL and GTL but with different out-put levels and receiver thresholds. The GTLP output LOWlevel is typically less than 0.5V, the output HIGH level is1.5V and the receiver threshold is 1.0V.
Features |
| Bidirectional interface between GTL/GTLP and LVTTLlogic levels Output Edge Rate Control to minimize noise on theGTLP port Power up/down/off high impedance for live insertion Standard 245 function CMOS technology for low power dissipation 5V tolerant inputs and outputs on the A-Port Bus-hold data inputs on the A-Port eliminates the need for external pull-up resistors on unused inputs LVTTL compatible driver and control inputs Flow through pinout optimizes PCB layout Open drain on GTLP to support wired-or connection A-Port source/sink −24 mA/+24 mA B-Port sink 50 mA Recommended Operating Temperature −40 to +85 |